Embodiments of the present invention relate to etching processes for double patterning features.
Electronic circuits, such as integrated circuits, display circuits, memory circuits, power circuits, and photovoltaic circuits (e.g., solar cells) are being made ever smaller to increase portability, computing power or power output. Thus, the sizes of the active and passive features of these circuits, such as semiconducting features, gates, electrodes, resistors, memories, interconnects, and photovoltaic cells, are also becoming ever smaller. Features are being dimensioned at 65 nm or even 45 nm or smaller and new processes are being developed to make features with even smaller geometries. For example, double patterning (DP) processes use multiple lithography processing steps to obtain features with smaller dimensions—for example, exemplary double patterning processes are described in commonly assigned US Patent Publication No. 2009/0117491 to Hendel et al. filed on Aug. 17, 2008, entitled “Resolution Enhancement Techniques Combining Interference-Assisted Lithography with other Photolithography Techniques”, which is incorporated by reference herein and in its entirety.
In the fabrication of DP features, silicon-containing dielectric materials are used as etch-stop layers to protect underlying features and form overlying spacers or gap fillers between metal lines, vias, and memory elements. Commonly-used silicon-containing dielectric features are composed of silicon dioxide, silicon nitride and silicon oxy-nitride. In the DP process, the deposited dielectric features need to be etched without damaging surrounding and underlying features. For example, in some applications, a dielectric feature that is an etch-stop layer is etched away after other features in the DP stack are etched. In other applications, portions of the dielectric feature are etched away while other portions are allowed to remain on the DP structure.
In conventional patterning processes, wet chemical etching processes are used to chemically etch the dielectric portions of conventional patterning features and thereafter the patterned substrate is rinsed and dried. The wet chemical etching processes allow etching of the dielectric features with controlled etch stop capabilities because the chemical etching process automatically terminates when the particular dielectric material being etched is entirely removed. The etch stop capabilities are important to prevent over etching of the dielectric portions of the features and subsequent etching into underlayers or surrounding materials. Conventional chemical solutions used in patterning processes to remove the dielectric layer include hydrofluoric acid or dilute hydrofluoric acid which can be a solution of hydrofluoric acid and deionized water, or hot phosphoric acid.
However, advanced DP features being currently developed have smaller width dimensions resulting in trenches or lines having high aspect ratios, and can be adversely affected by wet processing. In particular, the use of wet chemical diluted acid solutions to etch dielectric materials between or on such high aspect ratio features can result in variable etching rates for different dielectric. The variable etching rates can be a result of the surface tension of the wet chemical solution, which can impede effective etching in the narrow gaps between high aspect features. Further, severe feature line bending can occur during the drying step when the chemical etching liquid is removed or when the subsequent rinse liquid is removed from between the tight, high aspect ratio spaces, as illustrated in FIG. 1. Feature bending occurs because the high aspect ratio features are not strong enough to withstand surface tension forces during the drying process. In the drying process, the surface tension force applied by the liquid between the features is gradually removed as the liquid evaporates causing narrow dimensioned features to buckle. Quantitatively, the maximum tolerable sidewall deformation δ between features is given by the formula:
  δ  =      3    ⁢    σ    ⁢                  ⁢    cos    ⁢                  ⁢    θ    ⁢                  H        4                    dEL        3            where σ is the surface tension of the liquid, θ is the deformation angle at the top of the bent line pattern, between the meniscus of the drying liquid surface and the sidewall, H is the height of the feature, d is the spacing between adjacent high aspect ratio features, E is the Young's modulus and L is the thickness of the high aspect ratio feature.
Drying can also leave water marks if not done properly because the chemical reaction between the wet chemical agent and the dielectric material can leave behind a chemical residue that is not completely removed in the wet chemical etching process, nor by the subsequent rinse process. Still further, certain dielectric materials, such as silicon oxy-nitride, etch at much slower rates than non-nitride oxide features, and thermal oxide and annealed oxide features also etch at different rates compared to deposited oxide layers. This causes significant etching variability between the different features on a particular substrate.
Reactive ion etching (RIE) processes are dry etching processes that have been used to etch conventional dielectric materials, as for example described in commonly assigned US patent publication number 20090104782 A1, entitled “Selective Etching of Silicon Nitride”, by Lu et al. filed on Oct. 7, 2008, which is incorporated by reference herein in its entirety. However, in RIE etching processes, the plasma species energetically impinge on the substrate resulting in an etching process which has both a chemical etching and a physical bombardment component. The physical bombardment during conventional RIE etching processes can excessively etch and cause lattice damage in the dielectric layer. Further, as the RIE process relies on the kinetic energy of the etching species, RIE does not have a good etch selectivity and can excessively etch adjacent features. The poor selectivity of RIE further means that RIE processes can etch through features and into underlayers, which can be undesirable. For these reasons, conventional RIE processes are not being used for hard mask removal in DP feature fabrication processes.
For various reasons that include these and other deficiencies, and despite the development of various processes for etching portions of double patterning features, further improvements in such etching processes are continuously being sought.